SINGLE PIN CLOCK-FREE RETENTION FLIP-FLOP
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United States of America
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Issued Date -
Nov 28, 2024
app pub date -
May 16, 2024
filing date -
May 16, 2024
priority date (Note) -
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Abstract
A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.
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