LATCH, PROCESSOR INCLUDING LATCH, AND COMPUTING APPARATUS
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United States of America
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Issued Date -
Nov 28, 2024
app pub date -
Mar 9, 2023
filing date -
Mar 9, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.
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