LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240395825A1
SERIAL NO

18789755

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Abstract

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A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR ENERGY LABORATORY CO LTDKANAGAWA KEN 243-0036

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
ISOBE, Atsuo Isehara, JP 213 5332
TAMURA, Hikaru Hadano, JP 118 1870
UESUGI, Wataru Atsugi, JP 32 307

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