SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET)
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United States of America
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Issued Date -
Nov 28, 2024
app pub date -
Jul 31, 2024
filing date -
Jul 31, 2024
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Abstract
A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.
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