LOW POWER CLOCK INJECTION DURING IDLE MODE OPERATIONS
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United States of America
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Issued Date -
Nov 28, 2024
app pub date -
Aug 2, 2024
filing date -
Aug 2, 2024
priority date (Note) -
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Abstract
An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.
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