Importance

Loading Importance Indicators...

Abstract

A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. A respective data buffer includes data paths and logic configurable to, in response to the second module control signals, enable at least a subset of the data paths to receive and regenerate signals carrying a section of the data communicated from/to corresponding module data lines. The logic is further configurable to disable the data paths when the memory module is not communicating data with the memory controller.

Loading the Abstract Image...

First Claim