IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240388256A1
SERIAL NO

18622519

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.

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Patent Owner(s)

Patent OwnerAddress
PSEMI CORPORATION9369 CARROLL PARK DRIVE SAN DIEGO CA 92121

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
RANTA, Tero Tapio San Diego, US 114 1692

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