NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS
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United States of America
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Nov 21, 2024
app pub date -
May 20, 2024
filing date -
May 20, 2024
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Abstract
A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
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