THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OVERLYING THIN FILM TRANSISTOR CONTROL CIRCUIT AND METHOD OF MAKING THEREOF

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240387370A1
SERIAL NO

18361575

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Abstract

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A semiconductor structure includes a memory die and a logic die. The memory die includes a three-dimensional memory device that contains an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the two-dimensional array of memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel, a respective drain region, and a vertical stack of memory elements located at levels of the electrically conductive layers, memory-side bonding pads, and a first peripheral circuit including first thin film transistors located between the three-dimensional memory device and the memory-side bonding pads. The logic die includes a logic-side substrate, logic-side bonding pads bonded to the memory-side bonding pads, and a second peripheral circuit located between the logic-side substrate and the logic-side bonding pads.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES INC951 SANDISK DRIVE LEGAL DEP MILPITAS CA 95035

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DUNGA, Mohan Santa Clara, US 47 559
MAYUZUMI, Satoru Cupertino, US 32 228
NARAYANAN, Sudarshan San Jose, US 23 43

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