INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Nov 21, 2024
app pub date -
Jul 30, 2024
filing date -
Jul 30, 2024
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Abstract
A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second active region edges, calculating a gate resistance value based on the location and first and second active region edges, based on the resistance value, modifying the IC layout diagram by changing the location of the gate via along the gate region and/or adding another gate via positioned at another location along the gate region, and storing the modified IC layout diagram in a storage device.
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