METHOD AND SYSTEM FOR LATCH-UP PREVENTION

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240386180A1
SERIAL NO

18787493

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Abstract

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An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDHSIN-CHU

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Kuo-Ji Taipei county, TW 100 495
Chen, Wen-Hao Hsin-Chu City, TW 112 704
Islam, Rabiul Austin, US 17 242
Lai, Po-Chia Fremont, US 22 35
Li, Kuan-Te Taoyuan, TW 6 21
Lin, Wun-Jie Hsinchu City, TW 97 798
Rusu, Stefan Sunnyvale, US 192 1598
Scott, David Barry Plano, US 14 638
Su, Yu-Ti Tainan City, TW 80 242
Ying, Shu-Yi Hsinchu County, TW 11 47

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