SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
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United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Jul 23, 2024
filing date -
Jul 23, 2024
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Abstract
The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.
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