ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL)
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Jul 23, 2024
filing date -
Jul 23, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.
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