CHECKERBOARD DUMMY DESIGN FOR EPITAXIAL OPEN RATIO
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United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Jul 22, 2024
filing date -
Jul 22, 2024
priority date (Note) -
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Abstract
Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.
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