SEMICONDUCTOR STRUCTURE WITH PULL-IN PLANARIZATION LAYER AND METHOD FORMING THE SAME
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United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Jul 22, 2024
filing date -
Jul 22, 2024
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Abstract
A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.
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