MEMORY DEVICE THAT INCLUDES A DUTY CORRECTION CIRCUIT, MEMORY CONTROLLER THAT INCLUDES A DUTY SENSING CIRCUIT, AND STORAGE DEVICE THAT INCLUDES A MEMORY DEVICE
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United States of America
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Issued Date -
Nov 14, 2024
app pub date -
Jul 23, 2024
filing date -
Jul 23, 2024
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status (Latency Note)
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Abstract
A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
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