Importance

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Abstract

A power-efficient and clock-shaping clock structure for a digital semiconductor device. The device can include an array of logic blocks. A root-column clock trace is coupled to column-clock traces extending along each column of the array. The clock traces feed the logic block at evenly spaced points to control the delay time for the execution of the logic blocks. The root-column clock trace is fed a clock from a single endpoint that result in a propagation wave of logic blocks execution. The clock structure can include row-clock traces placed across the array rows and coupled to a root-row clock trace. Each logic block can receive a clock from the intersection of the column-clock trace and the row-clock trace. A clock input at a single point where the root-column clock trace and root-row clock trace meet.

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First Claim