SEMICONDUCTOR DEVICE HAVING DOPANT DEACTIVATION UNDERNEATH GATE
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United States of America
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Nov 7, 2024
app pub date -
Jul 12, 2024
filing date -
Jul 12, 2024
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Abstract
A transistor includes a substrate. The transistor further includes a channel region comprising dopants of a first type. The transistor further includes a gate structure over the channel region. The transistor further includes a source comprising dopants of a second type. The transistor further includes a lightly doped drain (LDD) comprising dopants of the second type, wherein the LDD is over the source, and the channel region is in direct contact with the LDD. The transistor further includes a deactivated region in the channel region underneath the gate structure, wherein the deactivated region comprises a first region inside an epitaxial layer and a second region outside the epitaxial layer.
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