DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL
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United States of America
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Nov 7, 2024
app pub date -
Jul 19, 2024
filing date -
Jul 19, 2024
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Abstract
The present disclosure, in some embodiments, relates to a method for generating a scaled integrated chip design. The method includes forming an original integrated chip (IC) design including a graphical representation of a layout corresponding to an integrated chip to be formed on a semiconductor substrate. The original IC design includes a gate contact layer having a plurality of gate contacts and a first interconnect layer having a first plurality of interconnects. The gate contact layer is scaled at a first scaling ratio, and the first interconnect layer is scaled at a second scaling ratio that is different than the first scaling ratio.
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