D FLIP-FLOP, PROCESSOR INCLUDING THE D FLIP-FLOP, AND COMPUTING APPARATUS
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United States of America
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Issued Date -
Oct 31, 2024
app pub date -
Mar 6, 2023
filing date -
Mar 6, 2023
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Abstract
The present disclosure relates to a D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.
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