MINIMIZATION OF SILICON GERMANIUM FACETS IN PLANAR METAL OXIDE SEMICONDUCTOR STRUCTURES
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United States of America
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Oct 31, 2024
app pub date -
Jul 8, 2024
filing date -
Jul 8, 2024
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Abstract
A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
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