SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO GATE STRUCTURE ON PMOS REGION
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Oct 31, 2024
app pub date -
Jul 4, 2024
filing date -
Jul 4, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully