SYSTEM AND METHOD FOR PROCESSING BOOLEAN AND GARBLED CIRCUITS IN MEMORY-LIMITED ENVIRONMENTS
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United States of America
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Oct 31, 2024
app pub date -
Jul 10, 2024
filing date -
Jul 10, 2024
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Abstract
Arrangements for use in garbling a circuit in a memory-limited environment, comprising: initializing auxiliary garbling data comprising a plurality of data features associated with execution of garbling operations for the entirety of the circuit being. initializing a plurality of input gates and a plurality of state gates; generating a circuit slice for an update function; setting the plurality of state gates as a plurality of new output-state-gates; generating a circuit slice for a finalization function, wherein the finalization function represented by a sub-circuit, the outputs of which are terminal gates; garbling the circuit slice generated for the finalization function to create a garbled circuit slice; and transmitting the garbled circuit slice substantially no later than completion of its creation; wherein initializing auxiliary garbling data is performed only once for the circuit and prior to initializing the plurality of input gates and the plurality of state gates.
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