THREAD SCHEDULING OVER COMPUTE BLOCKS FOR POWER OPTIMIZATION

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240362741A1
SERIAL NO

18662337

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Abstract

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One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Appu, Abhishek R El Dorado Hills, US 561 2990
Koker, Altug El Dorado Hills, US 565 3602
Ray, Joydeep Folsom, US 614 3794
Valerio, James A Hillsboro, US 30 247
Vembu, Balaji Folsom, US 330 2925

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