DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE
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United States of America
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Issued Date -
Oct 31, 2024
app pub date -
Apr 15, 2024
filing date -
Apr 15, 2024
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Abstract
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
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