TIME-TO-DIGITAL CONVERTERS (TDC) EMPLOYING A SINGLE-STAGE DELAY PAIR AND NOISE SHAPING FOR WIDE INPUT RANGE AND REDUCED QUANTIZATION NOISE IN A PHASE-LOCKED LOOP (PLL)

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United States of America

APP PUB NO 20240361729A1
SERIAL NO

18141342

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Abstract

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Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

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MICROSOFT TECHNOLOGY LICENSING LLCONE MICROSOFT WAY REDMOND WA 98052

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  • 2023 Application Filing Year
  • H03L Class
  • 302 Applications Filed
  • 126 Patents Issued To-Date
  • 41.73 % Issued To-Date
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Inventor Name Address # of filed Patents Total Citations
CHEN, Minhan Cary, US 24 158
LU, Ping Cary, US 97 984

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