TIME-TO-DIGITAL CONVERTERS (TDC) EMPLOYING A SINGLE-STAGE DELAY PAIR AND NOISE SHAPING FOR WIDE INPUT RANGE AND REDUCED QUANTIZATION NOISE IN A PHASE-LOCKED LOOP (PLL)
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Oct 31, 2024
app pub date -
Apr 28, 2023
filing date -
Apr 28, 2023
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Abstract
Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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MICROSOFT TECHNOLOGY LICENSING LLC | ONE MICROSOFT WAY REDMOND WA 98052 |
International Classification(s)

- 2023 Application Filing Year
- H03L Class
- 302 Applications Filed
- 126 Patents Issued To-Date
- 41.73 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
CHEN, Minhan | Cary, US | 24 | 158 |
# of filed Patents : 24 Total Citations : 158 | |||
LU, Ping | Cary, US | 97 | 984 |
# of filed Patents : 97 Total Citations : 984 |
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- H03L Class
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