Importance

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Abstract

Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.

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First Claim