ETCH BLOCK STRUCTURE FOR DEEP TRENCH ISOLATION RECESS CONTAINMENT
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United States of America Patent
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Issued Date -
Oct 24, 2024
app pub date -
Jul 3, 2023
filing date -
Jul 3, 2023
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Abstract
The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.
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