EM AND RF MITIGATION SILICON STRUCTURES IN STACKED DIE MICROPROCESSORS FOR DIE TO PLATFORM AND DIE-DIE RF NOISE SUPPRESSION

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20240355778A1
SERIAL NO

18758909

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
INTEL CORPCALIFORNIA USA CALIFORNIA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
JAIN, Amit Sherwood, US 258 2652
SHEKHAR, Sameer Portland, US 28 68

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation