CIRCUIT, MULTIPLIER-ADDER, AND CIRCUIT OPTIMIZATION METHOD
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United States of America Patent
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Issued Date -
Oct 24, 2024
app pub date -
Jun 28, 2024
filing date -
Jun 28, 2024
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Abstract
Examples of circuits, multiplier-adders, and circuit optimization methods are described. One example circuit includes a digital addition circuit and an analog addition circuit. The digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products. The plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values. The first bit position range refers to S bit positions of a product value of one of the first values and one of the second values. S is a positive integer. The product value is obtained by performing bitwise accumulation after a group of partial products are shifted.
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