HYBRID RATE INTERFACE TO REDUCE POWER CONSUMPTION AND AREA IN HIGH-SPEED DACS AND DIGITAL TRANSMITTERS
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United States of America Patent
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Issued Date -
Oct 17, 2024
app pub date -
Apr 11, 2023
filing date -
Apr 11, 2023
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Abstract
An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.
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