MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING
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United States of America Patent
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Issued Date -
Oct 17, 2024
app pub date -
Apr 8, 2024
filing date -
Apr 8, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.
First Claim
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Family
| Country | kind | publication No. | Filing Date |
|---|---|---|---|
| US | B2 | US9874898 | May 08, 2012 |
| WO | A2 | WO2012158392 | May 08, 2012 |
| US | B2 | US11068017 | Jan 05, 2018 |
| US | B2 | US11953934 | Jul 06, 2021 |
| US | A1 | US20250208645 | Jan 09, 2025 |
International Classification(s)
- 2024 Application Filing Year
- G06F Class
- 24496 Applications Filed
- 1771 Patents Issued To-Date
- 7.23 % Issued To-Date
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- G06F Class
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