Machine Learning Control of Clock Drift
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United States of America Patent
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Issued Date -
Oct 17, 2024
app pub date -
Jun 27, 2024
filing date -
Jun 27, 2024
priority date (Note) -
Published
status (Latency Note)
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Abstract
Systems and methods for controlling clock drift of an integrated circuit device are provided. Such a system may include a local oscillator to provide a reference clock signal, a phase-locked loop to provide a system clock signal based on the reference clock signal and a drift control signal, and processing circuitry to generate the drift control signal. In a synchronization mode, the processing circuitry may generate the drift control signal based on an input time reference signal. In a holdover mode, the processing circuitry may generate the drift control signal based on a trained machine learning model.
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