THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Jun 21, 2024
filing date -
May 18, 2020
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Abstract
A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region, a first electrode structure and a second electrode structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern is greater than a maximum width of the separation structure in the second direction.
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