CIRCUIT ARRANGEMENT, TIME-MODE ARITHMETIC UNIT, ALL-DIGITAL PHASE-LOCKED LOOP, AND CORRESPONDING METHODS
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Aug 5, 2022
filing date -
Aug 6, 2021
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Abstract
Examples relate to a circuit arrangement, a time-mode arithmetic unit circuit arrangement, an all-digital phase-locked loop, and corresponding methods. A circuit arrangement is configured to discard charges from a capacitive circuit element of the circuit arrangement based on a width of one or more signal pulses of an input signal being provided to the circuit arrangement, with the rate at which the charges are discarded being dependent on at least one control signal being provided to the circuit arrangement. The circuit arrangement is configured to provide an output signal flank having a delay relative to a readout signal flank being provided to the circuit arrangement, with the delay being based on the charges stored in the capacitive circuit element at the time the readout signal flank is provided to the circuit arrangement.
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