DELAY LOCKED LOOP

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United States of America Patent

APP PUB NO 20240340013A1
SERIAL NO

18311251

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A delay locked loop includes a delay line, a phase detector, a controller, an output clock generator, and a feedback circuit. The delay line receives an input clock signal and a control code, and generates a delayed clock signal by delaying the input clock signal according to the control code. The phase detector receives a reference clock signal and a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal to generate phase comparison information. The controller generates the control code and a switching signal according to the phase comparison information. The output clock generator selects the delayed clock signal or an inverted signal of the delayed clock signal according to the switching signal to generate an output clock signal. The feedback circuit generates the feedback clock signal according to the output clock signal.

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Patent Owner(s)

Patent OwnerAddress
WINBOND ELECTRONICS CORPNO 8 KEYA 1ST RD DAYA DISTRICT CENTRAL TAIWAN SCIENCE PARK TAICHUNG CITY

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sun, Chi-Hsiang Taichung City, TW 5 2

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