LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
May 26, 2023
filing date -
Apr 5, 2023
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Abstract
A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.
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