CLOCK DISTRIBUTION JITTER REDUCTION SYSTEMS AND METHODS
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Mar 8, 2024
filing date -
Apr 4, 2023
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Abstract
Embodiments of the invention relate to a clock generation and distribution circuit (“clock circuit”) according to various embodiments of the present disclosure. The clock circuit comprises active impedance reduction circuits which improves bandwidth and jitter performance of the clock circuit by lowering the small-signal impedance within the clock circuit. In certain embodiments, an activation element is positioned at a node along a transmission path to cause a reduction in impedance.
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