MANUFACTURING METHOD FOR LDMOS INTEGRATED DEVICE

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United States of America Patent

APP PUB NO 20240339522A1
SERIAL NO

18292067

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.

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Patent Owner(s)

Patent OwnerAddress
CSMC TECHNOLOGIES FAB2 CO LTD214028 NO 8 XINZHOU ROAD NATIONAL HI TECH INDUSTRIAL DEVELOPMENT ZONE WUXI JIANGSU WUXI CITY JIANGSU PROVINCE 214028

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CAO, Ruibin Wuxi, CN 2 0
CHEN, Shuxian Wuxi, CN 46 282
LIN, Feng Wuxi, CN 436 3851
MA, Chunxia Wuxi, CN 1 0
XU, Chaoqi Wuxi, CN 2 0
XU, Penglong Wuxi, CN 1 0
ZHANG, Yi Wuxi, CN 1881 15120

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