CONTAMINANT COLLECTION ON SOI
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Jun 20, 2024
filing date -
Feb 5, 2022
priority date (Note) -
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Abstract
An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.
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