INTEGRATING INPUT AND OUTPUT CAPACITANCE WITH HIGH FREQUENCY SHUNT CAPACITANCE ON A SINGLE ADDITIVELY MANUFACTURED SUBSTRATE
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Apr 7, 2023
filing date -
Apr 7, 2023
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Abstract
A package is described. The package includes a die covered by a lid. The lid maintains a hermetic seal for the die. The package includes high frequency shunt capacitance in parallel with surface-mount capacitors. The high frequency shunt capacitance is formed by interdigital capacitors below the surface-mount capacitors. The interdigital capacitors, the surface-mount capacitors, and the die form a circuit which produces a stable output voltage. The output voltage may remain stable even when subject to noise due to energized particles in space. The package includes solder resist with openings for attaching the surface-mount capacitors to the interdigital capacitors. Advantageously, the interdigital capacitors may achieve high frequency shunt capacitance on the order of nano-farads as part of the frame geometry with minimal increase in package height.
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