LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING A CAPACITOR AND CONSTANT CURRENT SINK
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Apr 4, 2023
filing date -
Apr 4, 2023
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Abstract
Circuitry and a method of operating a clock monitoring circuit for monitoring a clock signal is disclosed. The method comprises charging a first capacitor connected to a connection between a first pair of transistors and a voltage reference, charging a second capacitor connected to a connection between a second pair of transistors and to the voltage reference, sinking a current from the first and second pair of transistors with a constant current sink, and asserting a clock slow detect (CSD) signal when a voltage at the constant current sink drops below a threshold indicating durations of phases of the clock signal lengthen.
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