Adiabatic Stepwise Clock Architecture
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United States of America Patent
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Issued Date -
Oct 10, 2024
app pub date -
Apr 7, 2023
filing date -
Apr 7, 2023
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Abstract
Various implementations described herein are directed to a device having a clock driver that provides an adiabatic stepwise clock signal via an output node, and the clock driver may be coupled between a supply voltage and ground. Also, the device may have selectively switched stages with each selectively switched stage having a capacitor and a transistor coupled in series between the output node and ground. In some instances, each capacitor may refer to an auxiliary tank capacitor that is electrically isolated from each other auxiliary tank capacitor.
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