INTEGRATED CIRCUIT WITH FAULT REPORTING STRUCTURE
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United States of America Patent
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Issued Date -
Oct 3, 2024
app pub date -
Jun 10, 2024
filing date -
Apr 8, 2022
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Abstract
A power management integrated circuit (PMIC) chip for providing power loss protection to an application device. The PMIC chip may be adapted to co-work with a plurality sets of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.
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