USING EMBEDDED SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM
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United States of America
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Issued Date -
Oct 3, 2024
app pub date -
Mar 12, 2024
filing date -
Mar 12, 2024
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Abstract
One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.
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