Importance

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Abstract

The disclosure provides a semiconductor device including a plurality of reception circuit blocks each individually receiving a data signal, performing predetermined signal processing for the received data signal, and receiving a test mode signal for instructing a normal operation or a test operation. Each of the plurality of reception circuit blocks includes a PLL circuit generating a clock signal phase-synchronized with a data signal received by itself; a first selector selecting, based on the test mode signal, one of the clock signal generated by the PLL circuit of a different reception circuit block other than a reception circuit block of itself of the plurality of reception circuit blocks and the clock signal generated by the PLL circuit of the reception circuit block of itself, and a signal processing circuit performing the predetermined signal processing in synchronization with the clock signal selected by the first selector.

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First Claim