THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD THEREOF
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United States of America Patent
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Issued Date -
Sep 26, 2024
app pub date -
Jun 6, 2024
filing date -
Aug 29, 2019
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Abstract
A semiconductor structure includes a stack structure including interleaved conductive layers and dielectric layers, memory strings and slit structures extending through the stack structure, and top select gate cuts extending through the stack structure. At least two of the top select gate cuts are disposed between adjacent slit structures. One of the memory strings includes a memory film and a channel layer. The memory film includes a tunneling layer, a storage layer, and a blocking layer. Each of the top select gate cuts has a width smaller than a diameter of the memory strings.
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