METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

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United States of America Patent

APP PUB NO 20240322004A1
SERIAL NO

18497446

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Abstract

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A method of manufacturing an integrated circuit device includes forming, on a substrate, a fin-type active region and a stack structure in which sacrificial semiconductor layers and nanosheet semiconductor layers are alternately stacked one-by-one, forming a first local liner on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer, which is closest to the fin-type active region and expose sidewalls of other sacrificial semiconductor layers, forming a second local liner on the sidewall of the stack structure to cover the sidewalls of the other sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer, exposing the bottom sacrificial semiconductor layer by removing the first local liner, forming a bottom insulating space exposing a fin top surface of the fin-type active region by removing the bottom sacrificial semiconductor layer, and forming a bottom insulating structure in the bottom insulating space.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTDGYEONGGI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHA, Jihoon Suwon-si, KR 7 1
KO, Kihyung Suwon-si, KR 3 0
YOO, Jiho Suwon-si, KR 22 78

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