INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20240321859A1
SERIAL NO

18187782

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Abstract

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An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95052

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chao, Robin Portland, US 24 6
Chu, Tao Portland, US 48 25
Ghani, Tahir Portland, US 756 7842
Huang, Chiao-Ti Portland, US 29 4
Jang, Minwoo Portland, US 20 4
Luo, Yanbin Portland, US 17 13
Murthy, Anand S Portland, US 351 6235
Packan, Paul Hillsboro, US 17 430
Xu, Guowei Portland, US 69 186
Zhang, Feng Hillsboro, US 1002 28040

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