MEMORY DEVICE INCLUDING VOLTAGE AND TEMPERATURE SENSING CIRCUIT AND METHOD FOR MANAGING OPERATION THEREOF
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United States of America Patent
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Issued Date -
Sep 26, 2024
app pub date -
Oct 2, 2023
filing date -
Mar 24, 2023
priority date (Note) -
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Abstract
A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.
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